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syn1588® PCI NIC |
syn1588® PCIe NIC |
SYN1588®Ethernet Switch |
The standard PCI Ethernet network interface card, which is compatible to the IEEE1588 Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems. The board is intended for both prototyping and volume purposes. |
The standard PCI Express Ethernet network interface card, that is fully compatible to the IEEE1588 Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems. The board is intended for both prototyping and volume purposes. |
Precision Clock Synchronization with Oregano's 8-Port Ethernet Switch
The 8-port Ethernet switch, which features enhancements to the IEEE1588 Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems. The board is intended for small volumes or prototyping purposes. |
* standard PCI form factor
* 32-bit, 33 MHz PCI interface (suited for 3V3 and 5V PCI slots)
* four programmable user input/output signals on SMA connectors (trigger, 1pps, period, event)
* New! user programmable time stamper
* optionally high precision oscillators for syn1588® clock
* general purpose connector for expansion or prototyping
* driver software for Linux OS contained in shipment
* driver software for Windows XP OS available
* syn1588® PTP stack included as binary for Linux and Windows
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* 1-lane PCI Express low-profile card
* 10/100/1000 MBit/s Ethernet NIC<
* two user programmable input/output signals on SMA connectors (trigger, 1pps, period, event)
* New! user programmable time stamper
* optionally high precision OCXO oscillators to further improve long-term stability & accuracy
* driver software for Linux, Windows, Free BSD
* syn1588® PTP stack included as binary for Linux and Windows
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* eight 10/100 Mbit/s ports
* one uplink/management ports
* central FPGA (Altera EP2S30) performing all IEEE1588 operations
* dedicated Zarlink Ethernet switch ZL50411
* optional X-Board module connection for adding local software
* several general purpose headers
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syn1588®VIP |
syn1588® IP Cores |
syn1588® Layer 2 |
syn1588®VIP is a single chip IEEE1588 solution. Basically the unit may act like a GPS receiver in a system without the need for an antenna. It supplies a 1PPS pulse and a NMEA compatible data stream on the serial interface. |
A full range of clock cores, which are compatible to the IEEE1588 Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems. The IP cores differ in footprint, number of I/Os, interface, and supported features.
The IEEE1588 Standard's Precision Time Protocol (PTP) allows to precisely synchronize computer clocks in local area networks. Because of its high speed, low price, and widespread use, Ethernet is the preferred communication medium. It is supported by all of Oregano Systems' syn1588® clock cores via use of the Media Independent Interface (MII) or GMII. |
IEEE Layer 2 offers the smallest and thus cheapest clock synchronisation.
Since its publication in 2002, the IEEE1588 Standard for a Precision Clock Synchronization Protocol for Networked Measurement and Control Systems has sparked tremendous interest. It comes at no surprise though that with the latest revision of the standard in 2008 quite a number of new features and options have come into the official document. Among them is the normative specification of Transport of PTP over IEEE802.3 Ethernet in Annex F, also know as IEEE1588 Layer 2. |
* single chip IEEE1588 solution
* 10/100/1000 MBit/s network interface
* IEEE1588-2008 layer 3 and layer 2 support
* 1 PPS output, 1PPS or event input, frequency output
* remote maintenance via IEEE1588 management messages
* optionally high precision OCXO oscillators to further improve long-term stability & accuracy
* full evaluation board available
* evaluation board data available upon request: schematic, Gerber data, BOM
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* fully synchronous to the system clock
* all registers of the core operate with the rising clock edge
* well commented, well structured VHDL cource code
* small footprint and small I/O count
* serial peripheral interface (SPI) for clock control
* media independent interface (MII) for sync message detection
* one event input, one trigger output, one period output, one 1 pulse per second (PPS) output
* pipelined adder based clock for best synchronization results
* seperate receive and transmit timestamp FIFOs
* clock time format compatible to the IEEE1588 standard
* suited for FPGA as well as ASIC implementations
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